A problem of metastability exists in a system where synchronous signals are exchanged between different clock domains of the same clock frequency but an arbitrary phase relation between the clock signals. Data signals that may change their logical state every clock period need some temporary storage to ensure a stable state when they are latched. In addition, the time a bit resides in a memory may be critical in some systems. So, another problem is the latency introduced in the data path when data are exchanged between different clock domains.
A conventional solution to these problems is to use a FIFO memory as a temporary storage. For write and read operations, incremented/decremented pointers are used that are synchronized to only one of the clock signals. This is not a fail-safe solution. The mean time between failures (MTBF) is a figure that depends on the phase relation between the clock signals and the frequency at which the FIFO memory is operated.